2021-11-15 14:46:59 +00:00
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use std::ops::RangeInclusive;
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2021-12-18 23:00:42 +00:00
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use crate::utils::join_bytes;
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2021-11-15 23:52:44 +00:00
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use crate::rom::{ROM, load_rom};
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2021-11-01 18:04:09 +00:00
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use crate::ppu::{
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2021-11-15 16:25:30 +00:00
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PPU,
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2021-11-05 05:19:47 +00:00
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DMA_ADDRESS,
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2021-11-01 18:04:09 +00:00
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};
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2021-12-18 23:00:42 +00:00
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use crate::timer::Timer;
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2021-11-01 02:02:09 +00:00
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use crate::joypad::{Joypad, JOYPAD_ADDRESS};
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2021-12-18 23:00:42 +00:00
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use crate::sound::Sound;
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2021-11-26 02:13:55 +00:00
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use crate::interrupts::{
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Interrupts,
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INTERRUPT_ENABLE_ADDRESS,
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INTERRUPT_FLAG_ADDRESS,
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};
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2021-10-14 00:38:37 +00:00
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2021-11-15 14:46:59 +00:00
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pub const BANK_ZERO: RangeInclusive<u16> = 0x0000..=0x3FFF;
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pub const BANK_SWITCHABLE: RangeInclusive<u16> = 0x4000..=0x7FFF;
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pub const VIDEO_RAM: RangeInclusive<u16> = 0x8000..=0x9FFF;
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pub const EXTERNAL_RAM: RangeInclusive<u16> = 0xA000..=0xBFFF;
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pub const WORK_RAM_1: RangeInclusive<u16> = 0xC000..=0xCFFF;
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pub const WORK_RAM_2: RangeInclusive<u16> = 0xD000..=0xDFFF;
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pub const ECHO_RAM: RangeInclusive<u16> = 0xE000..=0xFDFF;
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pub const SPRITE_ATTRIBUTE_TABLE: RangeInclusive<u16> = 0xFE00..=0xFE9F;
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pub const NOT_USABLE: RangeInclusive<u16> = 0xFEA0..=0xFEFF;
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pub const IO_REGISTERS: RangeInclusive<u16> = 0xFF00..=0xFF7F;
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pub const HIGH_RAM: RangeInclusive<u16> = 0xFF80..=0xFFFE;
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2021-10-22 20:32:12 +00:00
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2021-10-14 00:38:37 +00:00
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pub struct Bus {
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2021-10-14 18:25:20 +00:00
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data: [u8; 0x10000],
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2021-11-19 22:11:27 +00:00
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pub rom: Box<dyn ROM>,
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2021-11-15 21:38:52 +00:00
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pub ppu: PPU,
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pub joypad: Joypad,
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pub timer: Timer,
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2021-11-26 01:09:17 +00:00
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pub sound: Sound,
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2021-11-26 02:13:55 +00:00
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pub interrupts: Interrupts,
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}
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impl Bus {
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pub fn new() -> Self {
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2021-11-12 16:18:09 +00:00
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let args: Vec<String> = std::env::args().collect();
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2021-11-17 15:12:11 +00:00
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#[cfg(not(test))]
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if args.len() < 2 {
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eprintln!("Please, specify a ROM file");
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2021-11-12 19:04:10 +00:00
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std::process::exit(1);
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}
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2021-11-19 22:11:27 +00:00
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let rom = match load_rom(&args.get(1).unwrap_or(&"".to_string())) {
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2021-10-14 00:38:37 +00:00
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Ok(rom) => rom,
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Err(err) => {
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eprintln!("Could not read ROM: {}", err);
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2021-11-12 19:04:10 +00:00
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std::process::exit(1);
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},
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};
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2021-11-15 22:25:43 +00:00
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let mut bus = Self {
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data: [0x00; 0x10000],
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rom,
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2021-11-15 21:38:52 +00:00
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ppu: PPU::new(),
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joypad: Joypad::new(),
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timer: Timer::new(),
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2021-11-26 01:09:17 +00:00
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sound: Sound::new(),
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interrupts: Interrupts::new(),
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};
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// Hardware registers after the bootrom
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bus.write(0xFF00, 0xCF);
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bus.write(0xFF01, 0x00);
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bus.write(0xFF02, 0x7E);
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bus.write(0xFF04, 0x18);
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bus.write(0xFF05, 0x00);
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bus.write(0xFF06, 0x00);
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bus.write(0xFF07, 0xF8);
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bus.write(0xFF0F, 0xE1);
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bus.write(0xFF40, 0x91);
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bus.write(0xFF41, 0x81);
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bus.write(0xFF42, 0x00);
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bus.write(0xFF43, 0x00);
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bus.write(0xFF44, 0x91);
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bus.write(0xFF45, 0x00);
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bus.write(0xFF46, 0xFF);
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bus.write(0xFF47, 0xFC);
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bus.write(0xFF4A, 0x00);
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bus.write(0xFF4B, 0x00);
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bus.write(0xFFFF, 0x00);
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bus
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2021-10-14 00:38:37 +00:00
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}
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pub fn read(&self, address: u16) -> u8 {
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2021-11-15 14:46:59 +00:00
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if BANK_ZERO.contains(&address) || BANK_SWITCHABLE.contains(&address) || EXTERNAL_RAM.contains(&address) {
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2021-11-19 22:11:27 +00:00
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return self.rom.read(address);
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2021-11-04 18:13:22 +00:00
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} else if address == INTERRUPT_ENABLE_ADDRESS || address == INTERRUPT_FLAG_ADDRESS {
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2021-11-26 02:13:55 +00:00
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return self.interrupts.read(address);
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} else if VIDEO_RAM.contains(&address) {
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return self.ppu.read_vram(address);
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} else if SPRITE_ATTRIBUTE_TABLE.contains(&address) {
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return self.ppu.read_oam(address);
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} else if PPU::is_io_register(address) {
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return self.ppu.get_register(address);
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2021-11-26 01:09:17 +00:00
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} else if Sound::is_io_register(address) {
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return self.sound.get_register(address);
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2021-11-05 05:19:47 +00:00
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} else if address == JOYPAD_ADDRESS {
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return self.joypad.read(self.data[address as usize]);
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} else if Timer::is_io_register(address) {
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return self.timer.get_register(address);
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2021-10-14 00:38:37 +00:00
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}
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2021-10-22 20:32:12 +00:00
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self.data[address as usize]
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}
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2021-10-16 00:18:00 +00:00
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pub fn read_16bit(&self, address: u16) -> u16 {
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2021-10-22 14:56:54 +00:00
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join_bytes(self.read(address.wrapping_add(1)), self.read(address))
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2021-10-16 00:18:00 +00:00
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}
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2021-10-14 00:38:37 +00:00
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pub fn write(&mut self, address: u16, data: u8) {
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2021-10-20 17:29:55 +00:00
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if address == 0xFF01 {
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2021-10-29 22:03:02 +00:00
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// print!("{}", data as char);
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2021-10-20 17:29:55 +00:00
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}
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2021-10-22 20:32:12 +00:00
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2021-11-15 14:46:59 +00:00
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if BANK_ZERO.contains(&address) || BANK_SWITCHABLE.contains(&address) || EXTERNAL_RAM.contains(&address) {
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2021-11-19 22:11:27 +00:00
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self.rom.write(address, data);
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2021-11-26 02:13:55 +00:00
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} else if address == INTERRUPT_ENABLE_ADDRESS || address == INTERRUPT_FLAG_ADDRESS {
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self.interrupts.write(address, data);
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2021-11-15 14:46:59 +00:00
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} else if WORK_RAM_1.contains(&address) || WORK_RAM_2.contains(&address) {
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2021-10-22 20:32:12 +00:00
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self.data[address as usize] = data;
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// Copy to the ECHO RAM
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if address <= 0xDDFF {
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2021-11-15 14:46:59 +00:00
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self.data[(ECHO_RAM.min().unwrap() + (address - WORK_RAM_1.min().unwrap())) as usize] = data;
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}
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} else if EXTERNAL_RAM.contains(&address) {
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2021-11-19 22:11:27 +00:00
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self.rom.write(address, data);
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} else if ECHO_RAM.contains(&address) {
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2021-10-22 20:32:12 +00:00
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self.data[address as usize] = data;
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self.data[(WORK_RAM_1.min().unwrap() + (address - ECHO_RAM.min().unwrap())) as usize] = data; // Copy to the working RAM
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2021-11-15 21:38:52 +00:00
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} else if Timer::is_io_register(address) {
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self.timer.set_register(address, data);
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2021-11-26 01:09:17 +00:00
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} else if Sound::is_io_register(address) {
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self.sound.set_register(address, data);
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2021-11-04 03:24:31 +00:00
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} else if address == JOYPAD_ADDRESS {
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let byte = self.data[address as usize];
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self.data[address as usize] = (data & 0b11110000) | (byte & 0b00001111);
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2021-11-15 16:25:30 +00:00
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} else if VIDEO_RAM.contains(&address) {
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2021-11-15 21:38:52 +00:00
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return self.ppu.write_vram(address, data);
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2021-11-15 16:25:30 +00:00
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} else if SPRITE_ATTRIBUTE_TABLE.contains(&address) {
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2021-11-15 21:38:52 +00:00
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return self.ppu.write_oam(address, data);
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2021-11-05 05:19:47 +00:00
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} else if address == DMA_ADDRESS {
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self.data[address as usize] = data;
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2021-11-15 16:25:30 +00:00
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let source = (data as u16) * 0x100;
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let mut count: u16 = 0;
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let oam_addr = SPRITE_ATTRIBUTE_TABLE.min().unwrap();
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2021-11-05 05:19:47 +00:00
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while count < 160 {
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2021-11-19 18:26:16 +00:00
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self.ppu.write_oam(oam_addr + count, self.read(source + count));
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2021-11-05 05:19:47 +00:00
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count += 1;
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}
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2021-11-15 21:38:52 +00:00
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} else if PPU::is_io_register(address) {
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self.ppu.set_register(address, data);
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2021-10-29 03:13:23 +00:00
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} else {
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self.data[address as usize] = data;
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2021-10-22 20:32:12 +00:00
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}
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2021-10-13 17:56:00 +00:00
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}
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2021-10-16 00:18:00 +00:00
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pub fn write_16bit(&mut self, address: u16, data: u16) {
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2021-10-19 14:53:50 +00:00
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let bytes = data.to_le_bytes();
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self.write(address, bytes[0]);
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2021-10-22 14:56:54 +00:00
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self.write(address.wrapping_add(1), bytes[1]);
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2021-10-16 00:18:00 +00:00
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}
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2021-10-13 17:56:00 +00:00
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}
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