Commit Graph

49 Commits

Author SHA1 Message Date
9b08306c96 Temporally omitting tests for SLA and SRA 2021-10-18 10:57:06 -05:00
d093aa483d One more test with bus 2021-10-18 10:33:59 -05:00
aad827f05f RR instruction 2021-10-18 10:25:45 -05:00
8d1a0f6f2f RL instruction 2021-10-18 10:13:23 -05:00
9adf41ee47 16bit substraction is not really needed 2021-10-18 08:44:22 -05:00
7c804029ad Some refactors 2021-10-18 08:28:19 -05:00
f148ee5ba6 Prefix CB RRC instruction 2021-10-17 21:45:55 -05:00
ec34a71fcf Mapping CB prefix instructions 2021-10-17 20:42:36 -05:00
3897c3561e add and sub instructions 2021-10-17 19:14:41 -05:00
a8f00f46fd more CALL instructions 2021-10-17 13:12:04 -05:00
31e0b2c79c Little refactor call instruction 2021-10-17 12:48:18 -05:00
ebadad803b Bug on LD instruction 2021-10-17 12:29:02 -05:00
e1d29d9530 Emulate Echo RAM 2021-10-17 12:02:33 -05:00
b3ba7b309e CP instruction 2021-10-17 10:55:16 -05:00
b098d28f0e AND, OR and XOR instructions 2021-10-16 22:38:13 -05:00
12b43ee985 Fix PUSH instruction 2021-10-16 20:50:31 -05:00
989971af8b Implement push and refactor pop 2021-10-16 19:41:07 -05:00
4dbcb4cb6c Update readme 2021-10-16 16:33:48 -05:00
d24f048c86 Another LD instruction 2021-10-16 14:50:01 -05:00
f94314ad01 Fix some bugs and implement a way to compare the logs 2021-10-16 14:17:28 -05:00
15e3d6685b Fix some bugs on instructions 2021-10-16 13:14:02 -05:00
afaecf597f Fix some tests, add a couple of new instructions and fix LD instruction bug 2021-10-15 20:59:35 -05:00
9d8d05c660 Including more test roms and initializing the registers 2021-10-15 19:49:36 -05:00
f9d5cfaa02 Refactor 16bit bus read write 2021-10-15 19:18:00 -05:00
891a72ad73 POP and RET instructions 2021-10-15 15:08:26 -05:00
0a1edfa39e More tests for INC and DEC with 16bit registers 2021-10-15 13:44:05 -05:00
c55256a5b7 Refactor register bit length detection 2021-10-15 09:49:35 -05:00
dbe95bedf2 Increment and decrement instructions 2021-10-14 23:58:51 -05:00
724cb27c49 Functions and tests for detecting half carry 2021-10-14 23:32:48 -05:00
b2190d1868 Refactor enums 2021-10-14 21:54:43 -05:00
253da76fd5 CALL u16 and RST instructions 2021-10-14 17:07:51 -05:00
d26b77dc78 Some refactors 2021-10-14 16:13:28 -05:00
a5fad87319 RLCA, LD and DI instructions 2021-10-14 13:25:20 -05:00
bc3b25857b Little refactor 2021-10-14 08:38:57 -05:00
92229e3d93 JP u16 instruction 2021-10-13 20:50:48 -05:00
5d04b7c346 Modeling the Bus and writing first test for NOP instruction 2021-10-13 19:38:37 -05:00
2afa2a1ff8 Memory maps 2021-10-13 12:56:00 -05:00
1902884df9 Logic to load a rom file 2021-10-12 19:11:52 -05:00
1e363187f1 Define test for CPU instructions (no tests yet) 2021-10-12 18:29:25 -05:00
f62926a869 Enum most opcode parameters (CB prefix remaining) 2021-10-12 18:06:07 -05:00
9bf80459a7 Add illegal instruction 2021-10-12 12:52:04 -05:00
bbf6b19957 Mapping opcodes 2021-10-11 20:38:37 -05:00
5e825a9298
Create LICENSE 2021-10-11 20:30:17 +00:00
0deee302ea Add readme 2021-10-11 14:51:24 -05:00
b6f512f97b Tests for registers getters and setters 2021-10-11 13:14:08 -05:00
d37699f4a8 Functions and tests for some bitwise operations and getter/setter for flag register 2021-10-11 12:58:09 -05:00
b3e6baaa3f Getters and setters for registers 2021-10-11 11:39:13 -05:00
9818c57854 Define CPU registers 2021-10-11 10:53:02 -05:00
c6246a9502 First commit 2021-10-11 09:57:30 -05:00